Various counter circuits are known in the art. As shown in FIG. 1, a typical prior art counting circuit includes an N-bit counting element 10, an input register 12 and an output register 14. The counter circuit operates as follows:
a) the input register 12 stores data from a data bus 16 upon receipt of both a WRITE signal and a proper address signal from an address bus 18 (i.e. an address which indicates counting element 10); PA1 b) the counting element 10 increases or decreases by one (1) the value of the data stored in the input register 12 and places the result in the output register 14; and PA1 c) the output register 14 provides the result to the data bus 16, via a buffer 20, upon receipt of a READ signal and a proper address signal. PA1 a) the read address decoder 34 decodes the register address indicated by the source address, asrc, and provides a READ signal to the indicated register, for example, register 2; PA1 b) the ALU 32 receives the contents of the indicated register and performs the desired counting operation, providing the result back to the register file array 30; and PA1 c) the write address decoder 36 decodes the register address indicated by the destination address, adst, and provides a WRITE signal to the indicated register, thereby causing the output of the ALU 32 to be written to the indicated register. Since adst and asrc are independent, they can indicate the same or different registers.
Since the counting rate of the counting element 10 is determined only by the frequency of a clock (CLK) signal, counting circuits such as those shown in FIG. 1 can provide relatively high counting rates. However, when a plurality of counting circuits are implemented into an integrated circuit design, they utilize an unacceptably large area of the integrated circuit as well as consuming an unacceptably large amount of power.
A more area-efficient prior art counting circuit 28 is shown in FIG. 2 and is described in the handbook Programmable System Devices PSD Design and Applications Handbook 1990, pp. 4-39--4-40. Circuit 28 is operative to perform many independent counting operations and comprises a multi-port register file array 30 connected to at least one arithmetic logic unit (ALU) 32. The register file array 30 comprises M N-bit registers 31, a read address decoder 34, a write address decoder 36 and independent source and destination address lines, asrc and adst, respectively.
Circuit 28 additionally includes communication elements (not shown) with which data is provided to and received from a data bus.
It is noted that there is a circular path, labeled 38, from the register file array 30, through the ALU 32, and back to the register file array 30.
The alternative counting circuit operates as follows:
As is known in the art, the ALU 32 typically receives no start or stop signals. Rather, it continually operates, regardless of the data which is provided to it, and it continually provides results. Thus, when the read/modify/write operations described hereinabove modify a single register and are performed within a single clock cycle, it is possible for ALU 32 to provide results to the register before the read operation finishes. The write operation will corrupt the data being read which, in turn causes the data received by the ALU 32 to be incorrect which, in turn, causes the data written into the register to be incorrect. This situation is known as a "race condition" and is highly undesirable.
The race condition is typically overcome with special circuits that carefully control the timing of the read and write signals such that the read operation finishes before the write operation ever begins. In order for this solution to operate in the face of temperature and process variations, margins must be added to the time allocated for each of the read and write operations. These margins directly add to the overall time required to execute the read/modify/write operation, resulting in a tradeoff between the risk of having a race condition occur and the speed of the operation.
A race-free operation cycle typically can be determined for a given operating frequency; however, if the circuit has to be operated at a different (slower or faster) frequency for any reason, such as when it is placed in a different environment or when it is being tested, the circuit will not operate properly.
Thus, although the register file array--ALU counting circuit utilizes less power and area, it typically operates at slower speeds than the standard logic counting circuit and is not easily incorporated into environments with different operating frequencies.